Semiconductor integrated-circuit (IC) manufacturers face growing challenges to reliably produce ever-smaller transistors in order to improve performance and decrease cost. Many issues arise, though, when scaling devices such as, for example, FETs and more particularly MOSFETs (metal-oxide-semiconductor field effect transistors). For example, as MOSFETs are scaled below 100 nm in minimum lateral dimension, size-related performance and manufacturing issues become increasingly significant.
More specifically, short gate lengths in MOSFETs result in relatively large source-to-drain leakage currents. These leakage currents can result in undesirably large static power consumption. To suppress source-to-drain leakage current, it is possible to increase the net dopant concentration in the channel region, increase gate capacitance, and decrease the depths of the source and drain junctions adjacent to the channel. For example, a high net dopant concentration in the channel region confines the drain-induced lateral electric field to the drain region, thereby minimizing the effect of drain bias on the electric potential in the channel region near to the source. By increasing the capacitive coupling between the gate electrode and the channel region, control over the on and off state of the device is maintained by the gate electrode rather than the drain. This allows the gate-induced electric field to more effectively suppress source-to-drain leakage current. Also, by keeping the depths of the source and drain junctions adjacent to the channel shallower than the length of the channel region, sub-surface leakage currents can be suppressed.
Issues still arise with each of these approaches that need to be addressed. For example, decreasing the gate dielectric thickness leads to undesirable leakage between the gate electrode and channel region. Also, carrier mobility in small channel regions of MOSFETs can be degraded by high dopant concentration. This, in turn, results in lower “on-current” for the transistor. Moreover, the parasitic series resistance of the source and drain regions increases with decreasing junction depth, which results in lower on-current for the transistor. Accordingly, approaches designed to reduce static power consumption can negatively affect overall device performance.
Another issue is dimensional variations which may affect sensitivity of device performance. For example, relatively small differences in gate length can result in significant performance differences. However, the manufacturing processes used to create devices are unable to provide device-to-device dimensional consistency required to render such performance differences negligible. Consequently, circuit designers must design for worst-case scenarios to accommodate the wide range of device performance levels, thereby sacrificing overall performance to accommodate manufacturability concerns.
Another issue in device performance variation results from geometrical irregularity. For example, sidewall gating at the edges of the active regions due to a slightly recessed device-isolation material (typically silicon dioxide) results in threshold-voltage variation with channel width. This is because the channel is turned on at a lower gate voltage at the edges. Also, stresses in the MOSFET channel region depend on channel width as well as the device layout pattern and density, resulting in undesirable variations in transistor on-state current.
Accordingly, there exists a need in the art to overcome the deficiencies and limitations described hereinabove.